The art of integrated circuit fabrication has long pressed for reducing the dimensions of structures beyond (below) the nominal limits of the steppers and etching processes, referred to as sub-lithographic structures because the dimensions being fabricated are smaller than the current ground rules.
A well developed method of forming sub-lithographic gates for field effect transistors is the sidewall image transfer method in which a sidewall spacer (such as silicon nitride (Si3N4), for example) having a thickness less than that permitted by the current ground rules is formed on the sides of a sacrificial structure that is later removed.
The remaining sidewall spacer after removal of the sacrificial structure is used as a hardmask to etch the layers(s) below with a directional reactive ion etch. Since the sidewall has a (sublithographic) width less than the ground rules, the structure formed in the layer below will also have a sub-lithographic width. An example is shown in IEEE Transactions on Electron Devices, vol 49, March 2002, p436-441.
The sidewall material is selected to deposit conformally in order to maintain a desired width and to be etch resistant, to act as a hardmask. The layer below is selected to have appropriate electrical properties. As a common example, the sidewall spacer is silicon nitride and the layer below is polysilicon (poly).
As structure dimensions shrink, process variations that were previously insignificant become important, and the conventional sidewall image transfer process suffers from excessive variation across the circuit (across chip linewidth variation—ACLV). The conventional sidewall image transfer approach has difficulties, such as a) etch loading effects that cause variations in the spacer width due to pattern density or pattern pitch changes; and b) sputtering of the spacer during spacer etch creates sloped and asymmetric profiles, which can lead to image variation across the substrate.
The art would benefit from a sublithographic process having less variation in dimension.